vivado用(* MARK_DEBUG="true" *)抓信号问题请教

为什么我想抓如下用(* MARK_DEBUG="true" *)定义的信号抓不到?
reg [7:0] raw_u_gauss[0:505];
(* MARK_DEBUG="true" *)wire [7:0] raw_u_gauss_0;
(* MARK_DEBUG="true" *)wire [7:0] raw_u_gauss_1;
(* MARK_DEBUG="true" *)wire [7:0] raw_u_gauss_2;
(* MARK_DEBUG="true" *)wire [7:0] raw_u_gauss_3;
(* MARK_DEBUG="true" *)wire [7:0] raw_u_gauss_22;
(* MARK_DEBUG="true" *)wire [7:0] raw_u_gauss_23;
(* MARK_DEBUG="true" *)wire [7:0] raw_u_gauss_24;
(* MARK_DEBUG="true" *)wire [7:0] raw_u_gauss_25;
assign raw_u_gauss_0 = raw_u_gauss[0];
assign raw_u_gauss_1 = raw_u_gauss[1];
assign raw_u_gauss_2 = raw_u_gauss[2];
assign raw_u_gauss_3 = raw_u_gauss[3];
assign raw_u_gauss_22 = raw_u_gauss[22];
assign raw_u_gauss_23 = raw_u_gauss[23];
assign raw_u_gauss_24 = raw_u_gauss[24];
assign raw_u_gauss_25 = raw_u_gauss[25];

线网，被优化掉了，先keep住

是的 最终结果没用到

这些信号没有使用，在综合的时候被优化掉了。加一句KEEP = “ture”

不是vhdl才需要加keep吗?我verilog没加过keep啊。