用状态机写的串行数据接收程序,各种错误,附在后面,请各位前辈指教了
时间:10-02
整理:3721RD
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module v7(clk,rst,din,err,data_valid,data);
input clk,rst,din;
output err,data_valid,data;
reg err,data_valid;
reg[10:0] data;
reg [10:0] buffer;
reg [2:0] state;
reg temp;
reg [4:0] cnt;
parameter start_state='b00,data_state='b001,parity_state='b010,stop_state='b011,kong_state='b100;
initial begin
state=kong_state;
cnt<=0;
err<=0;
data_valid<=0;
end
always@(posedge clk or posedge rst)
begin
if (rst)
begin
state<=kong_state;
cnt=0;
err<=0;
data_valid<=0;
end
else if (din==1)
begin
state<=start_state;
case(state)
start_state:
begin
state<=data_state;
buffer(cnt)<=din; //expecting ';', found '<='
cnt=cnt+1;
end
data_state:
begin
for(cnt=1;cnt<=8;cnt=cnt+1)
buffer(cnt)<=din; //expecting ';', found '<='
if(cnt==9)
begin
state<=parity_state;
end
end
parity_state:
begin
temp<=(buffer(1)&&buffer(2)&&buffer(3)&&buffer(4)&&buffer(5)&&buffer(6)&&buffer(7)&&buffer(8));
buffer(9)<=temp; //expecting ';', found '<='
state<=stop_state;
end
stop_state:
if(din==1)
begin
err<=1;
data_valid<=1;
buffer(10)<=1; //expecting ';', found '<=',line 76 expecting 'end', found '1'
data<=buffer;
end
else
begin
err<=0; // line 81 expecting ':', found ';'
data_valid<=0; // line 82expecting ':', found ';'
data<='b00000000000; // line 83 expecting ':', found ';'
end
cnt<=0;
endcase
end
end
endmodule
input clk,rst,din;
output err,data_valid,data;
reg err,data_valid;
reg[10:0] data;
reg [10:0] buffer;
reg [2:0] state;
reg temp;
reg [4:0] cnt;
parameter start_state='b00,data_state='b001,parity_state='b010,stop_state='b011,kong_state='b100;
initial begin
state=kong_state;
cnt<=0;
err<=0;
data_valid<=0;
end
always@(posedge clk or posedge rst)
begin
if (rst)
begin
state<=kong_state;
cnt=0;
err<=0;
data_valid<=0;
end
else if (din==1)
begin
state<=start_state;
case(state)
start_state:
begin
state<=data_state;
buffer(cnt)<=din; //expecting ';', found '<='
cnt=cnt+1;
end
data_state:
begin
for(cnt=1;cnt<=8;cnt=cnt+1)
buffer(cnt)<=din; //expecting ';', found '<='
if(cnt==9)
begin
state<=parity_state;
end
end
parity_state:
begin
temp<=(buffer(1)&&buffer(2)&&buffer(3)&&buffer(4)&&buffer(5)&&buffer(6)&&buffer(7)&&buffer(8));
buffer(9)<=temp; //expecting ';', found '<='
state<=stop_state;
end
stop_state:
if(din==1)
begin
err<=1;
data_valid<=1;
buffer(10)<=1; //expecting ';', found '<=',line 76 expecting 'end', found '1'
data<=buffer;
end
else
begin
err<=0; // line 81 expecting ':', found ';'
data_valid<=0; // line 82expecting ':', found ';'
data<='b00000000000; // line 83 expecting ':', found ';'
end
cnt<=0;
endcase
end
end
endmodule
太多的基本知识错误~
能加个好友么,指点一下。