经过QUARTUS生成的tb文件如何写
这是用VHDL编程的SVPWM控制算法
=======================顶层文件===================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY svpwm IS
PORT
(
clk: IN STD_LOGIC;
Ts: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uab: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ubc: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uca: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ud: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p1: OUT STD_LOGIC;
p2: OUT STD_LOGIC;
p3: OUT STD_LOGIC;
p4: OUT STD_LOGIC;
p5: OUT STD_LOGIC;
p6: OUT STD_LOGIC
);
END svpwm;
ARCHITECTURE bdf_type OF svpwm IS
COMPONENT triangular_carrier
PORT(clk: IN STD_LOGIC;
Ts : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
carrier : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT switch_time
PORT(Tx: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ty : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Th : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Tl : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Tm : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT sector
PORT(Uab: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ubc : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uca : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT vector_time
PORT(N: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ts : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uab : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ubc : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uca : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ud : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Tx : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
Ty : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT pulse
PORT(carrier: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Th : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Tm : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
p1 : OUT STD_LOGIC;
p2 : OUT STD_LOGIC;
p3 : OUT STD_LOGIC;
p4 : OUT STD_LOGIC;
p5 : OUT STD_LOGIC;
p6 : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL SYNTHESIZED_WIRE_0: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_1: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_8: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_3: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_5: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_6: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL SYNTHESIZED_WIRE_7: STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
b2v_inst : triangular_carrier
PORT MAP(clk => clk,
Ts => Ts,
carrier => SYNTHESIZED_WIRE_3);
b2v_inst1 : switch_time
PORT MAP(Tx => SYNTHESIZED_WIRE_0,
Ty => SYNTHESIZED_WIRE_1,
Th => SYNTHESIZED_WIRE_5,
Tl => SYNTHESIZED_WIRE_6,
Tm => SYNTHESIZED_WIRE_7);
b2v_inst2 : sector
PORT MAP(Uab => Uab,
Ubc => Ubc,
Uca => Uca,
N => SYNTHESIZED_WIRE_8);
b2v_inst3 : vector_time
PORT MAP(N => SYNTHESIZED_WIRE_8,
Ts => Ts,
Uab => Uab,
Ubc => Ubc,
Uca => Uca,
Ud => Ud,
Tx => SYNTHESIZED_WIRE_0,
Ty => SYNTHESIZED_WIRE_1);
b2v_inst4 : pulse
PORT MAP(carrier => SYNTHESIZED_WIRE_3,
N => SYNTHESIZED_WIRE_8,
Th => SYNTHESIZED_WIRE_5,
TI => SYNTHESIZED_WIRE_6,
Tm => SYNTHESIZED_WIRE_7,
p1 => p1,
p2 => p2,
p3 => p3,
p4 => p4,
p5 => p5,
p6 => p6);
END bdf_type;
===========测试文件=========================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY svpwm_vhd_tst IS
END svpwm_vhd_tst;
ARCHITECTURE svpwm_arch OF svpwm_vhd_tst IS
--constants
-- signals
SIGNAL clk : STD_LOGIC:='0';
SIGNAL p1 : STD_LOGIC;
SIGNAL p2 : STD_LOGIC;
SIGNAL p3 : STD_LOGIC;
SIGNAL p4 : STD_LOGIC;
SIGNAL p5 : STD_LOGIC;
SIGNAL p6 : STD_LOGIC;
SIGNAL Ts : STD_LOGIC_VECTOR(31 DOWNTO0):="00000000000000000000000000000000";
SIGNAL Uab : STD_LOGIC_VECTOR(31 DOWNTO0):="00000000000000000000000000000000";
SIGNAL Ubc : STD_LOGIC_VECTOR(31 DOWNTO 0):="00000000000000000000000000000000";
SIGNAL Uca : STD_LOGIC_VECTOR(31 DOWNTO0):="00000000000000000000000000000000";
SIGNAL Ud : STD_LOGIC_VECTOR(31 DOWNTO0):="00000000000000000000000000000000";
COMPONENT svpwm
PORT(
clk: IN STD_LOGIC;
p1: OUT STD_LOGIC;
p2: OUT STD_LOGIC;
p3: OUT STD_LOGIC;
p4: OUT STD_LOGIC;
p5: OUT STD_LOGIC;
p6: OUT STD_LOGIC;
Ts: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uab: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ubc: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Uca: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Ud: IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
BEGIN
i1: svpwm
PORTMAP (
-- list connections between master portsand signals
clk=> clk,
p1=> p1,
p2=> p2,
p3=> p3,
p4=> p4,
p5=> p5,
p6=> p6,
Ts=> Ts,
Uab=> Uab,
Ubc=> Ubc,
Uca=> Uca,
Ud=> Ud
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END svpwm_arch;
====================================================
要求激励是
Clock High Time=500(ns)，
Clock Low Time=500(ns)，
Input Setup Time = 0(ns)，
Output Valid Delay=0(ns)，
Offset=0(ns)，
Single Clock=clk，
Initial Length of Test Bench=38400000(ns)，
Time Scale=ns。
Ts输入值为300(ns)。
Ud输入值为128(V)。
Uab,Ubc,Uca输入三相对称正弦电压值(V)：
Uab(t)=128sin(327t+120°)
Ubc(t)=128sin327t
Uca(t)=128sin(327t+240°)
请问测试文件中该如何写
已退回3积分