代码不懂求解释
时间：10-02
整理：3721RD
点击：
//分频单元
module clock_divder(
input sys_rstn,
input clk_50M ,
output reg clk_50Hz
);
reg [31:0] cnt;
always @(posedge clk_50M or negedge sys_rstn)
if (！sys_rstn)
cnt = 32'd5)//(cnt >= 32'd499999)
cnt = 32'd5)//(cnt >= 32'd499999)
clk_50Hz <= ~clk_50Hz;
endmodule
module clock_divder(
input sys_rstn,
input clk_50M ,
output reg clk_50Hz
);
reg [31:0] cnt;
always @(posedge clk_50M or negedge sys_rstn)
if (！sys_rstn)
cnt = 32'd5)//(cnt >= 32'd499999)
cnt = 32'd5)//(cnt >= 32'd499999)
clk_50Hz <= ~clk_50Hz;
endmodule
哪不懂?我手机端看不到完整的代码
输入50M时钟，每次时钟一个上升沿记一次数，每次记到5，重新从0计数，说以说你是分频50/6=8.33M 输出波形