新人请教一个时序问题
module triangle(clk_75M,rst,en_10K,q);
input clk_75M;
input rst;
output reg en_10K;
output reg [15:0] q; //16Q0 format
always @ (posedge clk_75M or posedge rst)
begin
if(rst)
q<=0;
else if(en_10K==0)
begin
if(q==16'd3750)
en_10K<=1;
else
q<=q+16'd1;
end
else if(q==0)
en_10K<=0;
else
q<=q-16'd1;
end
endmodule
用modelsin-ase做RTL仿真波形如下:
怎么去掉3750和0多余的一个时钟周期
刚刚突发奇想,自己搞定了,想知道,怎么删帖
module triangle(clk_75M,rst,en_10K,q);
input clk_75M;
input rst;
output reg en_10K;
output reg [15:0] q; //16Q0 format
always @ (posedge clk_75M or posedge rst)
begin
if(rst)
q<=0;
else if(en_10K==0)
begin
if(q==16'd3750)
begin
en_10K<=1;
q<=q-16'd1;
end
else
q<=q+16'd1;
end
else if(q==0)
en_10K<=0;
q<=q+16'd1;
else
q<=q-16'd1;
end
endmodule