求助：一个数组定义，老是提示缺少is

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity zdshj is
port(clk:in std_logic;
     set,buy,sel,finish:in std_logic;
          coin1,coin5:in std_logic;
          money1,money5:out std_logic;
          price,quantity:in std_logic_vector(3 downto 0);
          display,act:out std_logic_vector(3 downto 0);
          y0,y1:out std_logic_vector(6 downto 0));
end zdshj;
architecture behav of zdshj
#type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0)
#signal ram:ram_type;
signal clk1:std_logic;
signal item:std_logic_vector(1 downto 0);
signal cnt:std_logic_vector(3 downto 0);
signal pri,qua:std_logic_vector(3 downto 0);
begin
P0:process(set,clk1)
variable quan:std_logic_vector(3 downto 0);
begin
if set='1' then
        ram(conv_integer(item)) "0000" and cnt>=pri then
                   cnt "0101" then
              money5 "0000" then
              money1 display0 display0 display0 display0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y0 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1 y1<="1111111";
end case;
end process code2;
end behav;

就是有#号的两句，编译提示是Error (10500): VHDL syntax error at zdshj.vhd(15) near text "type";  expecting "is"