DE2-70 EP2C70F896C6 数码管引脚分配的时候段码是否公用?
时间:10-02
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DE2-70 EP2C70F896C6 数码管引脚分配的时候段码不是公用的吧 如果编写8位数码管动态显示 该怎么写程序,下面这段程序不适用于DE2-70 EP2C70F896C6吧,DE2-70 手册里边8个数码管的段码是各用个的,我也没找到位码该怎么分配,帮帮忙
module scan_led(clk,rst,sm_seg,sm_bit);
input clk,rst;
output[7:0] sm_seg; //数码管段选择输出
output[7:0] sm_bit; //数码管位选择输出
reg[7:0] sm_seg; //数码管段选择输出寄存器
reg[7:0] sm_bit; //数码管位选择输出寄存器
reg[15:0] cnt_scan;//扫描频率计数器
reg[4:0] dataout_buf;
always@(posedge clk or negedge rst)
begin
if(!rst) begin
cnt_scan<=0;
end
else begin
cnt_scan<=cnt_scan+1'b1;
end
end
always @(cnt_scan)
begin
case(cnt_scan[15:13])
3'b000 :
sm_bit = 8'b1111_1110;
3'b001 :
sm_bit = 8'b1111_1101;
3'b010 :
sm_bit = 8'b1111_1011;
3'b011 :
sm_bit = 8'b1111_0111;
3'b100 :
sm_bit = 8'b1110_1111;
3'b101 :
sm_bit = 8'b1101_1111;
3'b110 :
sm_bit = 8'b1011_1111;
3'b111 :
sm_bit = 8'b0111_1111;
default :
sm_bit = 8'b1111_1110;
endcase
end
always@(sm_bit)
begin
case(sm_bit)
8'b1111_1110:
dataout_buf=0;
8'b1111_1101:
dataout_buf=1;
8'b1111_1011:
dataout_buf=2;
8'b1111_0111:
dataout_buf=3;
8'b1110_1111:
dataout_buf=4;
8'b1101_1111:
dataout_buf=5;
8'b1011_1111:
dataout_buf=6;
8'b0111_1111:
dataout_buf=7;
default:
dataout_buf=8;
endcase
end
always@(dataout_buf)
begin
case(dataout_buf)
4'h0: sm_seg = 8'hc0; // "0"
4'h1 : sm_seg = 8'hf9; // "1"
4'h2 : sm_seg = 8'ha4; // "2"
4'h3 : sm_seg = 8'hb0; // "3"
4'h4 : sm_seg = 8'h99; // "4"
4'h5 : sm_seg = 8'h92; // "5"
4'h6 : sm_seg = 8'h82; // "6"
4'h7 : sm_seg = 8'hf8; // "7"
4'h8 : sm_seg = 8'h80; // "8"
4'h9 : sm_seg = 8'h90; // "9"
4'ha : sm_seg = 8'h88; // "a"
4'hb : sm_seg = 8'h83; // "b"
4'hc : sm_seg = 8'hc6; // "c"
4'hd : sm_seg = 8'ha1; // "d"
4'he : sm_seg = 8'h86; // "e"
4'hf : sm_seg = 8'h8e; // "f"
endcase
end
endmodule
module scan_led(clk,rst,sm_seg,sm_bit);
input clk,rst;
output[7:0] sm_seg; //数码管段选择输出
output[7:0] sm_bit; //数码管位选择输出
reg[7:0] sm_seg; //数码管段选择输出寄存器
reg[7:0] sm_bit; //数码管位选择输出寄存器
reg[15:0] cnt_scan;//扫描频率计数器
reg[4:0] dataout_buf;
always@(posedge clk or negedge rst)
begin
if(!rst) begin
cnt_scan<=0;
end
else begin
cnt_scan<=cnt_scan+1'b1;
end
end
always @(cnt_scan)
begin
case(cnt_scan[15:13])
3'b000 :
sm_bit = 8'b1111_1110;
3'b001 :
sm_bit = 8'b1111_1101;
3'b010 :
sm_bit = 8'b1111_1011;
3'b011 :
sm_bit = 8'b1111_0111;
3'b100 :
sm_bit = 8'b1110_1111;
3'b101 :
sm_bit = 8'b1101_1111;
3'b110 :
sm_bit = 8'b1011_1111;
3'b111 :
sm_bit = 8'b0111_1111;
default :
sm_bit = 8'b1111_1110;
endcase
end
always@(sm_bit)
begin
case(sm_bit)
8'b1111_1110:
dataout_buf=0;
8'b1111_1101:
dataout_buf=1;
8'b1111_1011:
dataout_buf=2;
8'b1111_0111:
dataout_buf=3;
8'b1110_1111:
dataout_buf=4;
8'b1101_1111:
dataout_buf=5;
8'b1011_1111:
dataout_buf=6;
8'b0111_1111:
dataout_buf=7;
default:
dataout_buf=8;
endcase
end
always@(dataout_buf)
begin
case(dataout_buf)
4'h0: sm_seg = 8'hc0; // "0"
4'h1 : sm_seg = 8'hf9; // "1"
4'h2 : sm_seg = 8'ha4; // "2"
4'h3 : sm_seg = 8'hb0; // "3"
4'h4 : sm_seg = 8'h99; // "4"
4'h5 : sm_seg = 8'h92; // "5"
4'h6 : sm_seg = 8'h82; // "6"
4'h7 : sm_seg = 8'hf8; // "7"
4'h8 : sm_seg = 8'h80; // "8"
4'h9 : sm_seg = 8'h90; // "9"
4'ha : sm_seg = 8'h88; // "a"
4'hb : sm_seg = 8'h83; // "b"
4'hc : sm_seg = 8'hc6; // "c"
4'hd : sm_seg = 8'ha1; // "d"
4'he : sm_seg = 8'h86; // "e"
4'hf : sm_seg = 8'h8e; // "f"
endcase
end
endmodule
应该可以,我也是菜鸟,呵呵