麻烦问一下这个程序出现的错误怎么修改？

错误Error (10500): VHDL syntax error at CNT10_TB.vhd(21) near text "BEGIN";  expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"Error (10500): VHDL syntax error at CNT10_TB.vhd(27) near text "PROCESS";  expecting ";", or an identifier ("process" is a reserved keyword), or "architecture"
程序LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
ENTITY CNT10_TB IS
END CNT10_TB;
ARCHITECTURE ONE OF CTN10_TB IS
  COMPONENT CNT10
   PORT (CLK,REST,EN,LOAD : IN STD_LOGIC;
       DATA :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
   DOUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
   COUT :OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  END COMPONENT;
SIGNAL  CLK :STD_LOGIC :='0';
SIGNAL  RST :STD_LOGIC :='1';
SIGNAL  EN  :STD_LOGIC :='0';
SIGNAL  LOAD:STD_LOGIC :='1';
SIGNAL  DATA :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DOUT : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUT : STD_LOGIC;
CONSTANT CLK_P :TIME :=30 ns;
BEGIN
   U1: CNT10 PORT  MAP (CLK =>CLK, RST=>RST,EN=>EN,LOAD=>LOAD,
                       DATA=>DATA, DOUT=>DOUT, COUT=>COUT);
  PROCESS BEGIN
     CLK<='0';  WAIT FOR  CLK_P;
     CLK<='1';  WAIT  FOR  CLK_P;
  END PROCESS;
     RST <= '1' ,'0' AFTER 110 ns, '1' AFTER 114 ns;
     EN <= '0' ,'1' AFTER 110 ns ;
     LOAD <= '1' ,'0' AFTER 910 ns, '1' AFTER 940 ns;
     DATA <= "0100","0110" AFTER 400 ns,
                            "0111" AFTER 700ns,"0100" AFTER 1000 ns;
  END ONE;

看上面说关键字的问题，可能是前面库没有声明。