verilog程序问题，请各位大神帮助
时间：10-02
整理：3721RD
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我的程序三部分：1602显示-延时1s-两行对调显示，但是烧进板子里面，只有第一步有效，请问我哪里出了错?请大家给予指点和建议，谢 @xiuyaa
module LCD1602(clk, rs, rw, en,dat,LCD_N,LCD_P);
input clk;
output [7:0] dat;
output rs,rw,en,LCD_N,LCD_P;
//tri en;
reg e;
reg [7:0] dat;
reg rs;
reg [15:0] counter;
reg [7:0] current,next,current_clkr,next_clkr;
reg clkr;
reg [1:0] cnt=2'b00,cntr=2'b00;
reg [8:0] cnt_clkr=9'b0;
parameter set0=8'h00;
parameter set1=8'h01;
parameter set2=8'h02;
parameter set3=8'h03;
parameter set4=8'h04;
parameter set5=8'h05;
parameter dat0=8'h06;
parameter dat1=8'h07;
parameter dat2=8'h08;
parameter dat3=8'h09;
parameter dat4=8'h0A;
parameter dat5=8'h0B;
parameter dat6=8'h0C;
parameter dat7=8'h0D;
parameter dat8=8'h0E;
parameter dat9=8'h0F;
parameter dat10=8'h10;
parameter dat11=8'h11;
parameter dat12=8'h12;
parameter dat13=8'h13;
parameter dat14=8'h14;
parameter dat15=8'h15;
parameter dat16=8'h16;
parameter dat17=8'h17;
parameter dat18=8'h18;
parameter dat19=8'h19;
parameter dat20=8'h1A;
parameter dat21=8'h1B;
parameter dat22=8'h1C;
parameter dat23=8'h1D;
parameter dat24=8'h1E;
parameter dat25=8'h1F;
parameter dat26=8'h20;
parameter dat27=8'h2A;
parameter dat28=8'h2B;
parameter dat29=8'h2C;
parameter dat30=8'h2D;
parameter dat31=8'h2E;
parameter dat32=8'h2F;
parameter dat33=8'h30;
parameter dat34=8'h31;
parameter dat35=8'h32;
parameter dat36=8'h33;
parameter dat37=8'h34;
parameter dat38=8'h35;
parameter dat39=8'h36;
parameter dat40=8'h37;
parameter dat41=8'h38;
parameter dat42=8'h39;
parameter dat43=8'h3A;
parameter dat44=8'h3B;
parameter dat45=8'h3C;
parameter dat46=8'h3D;
parameter dat47=8'h3D;
parameter dat48=8'h3F;
parameter dat49=8'h40;
parameter dat50=8'h41;
parameter dat51=8'h42;
parameter dat52=8'h43;
parameter dat53=8'h44;
parameter dat54=8'h45;
parameter dat55=8'h46;
parameter set6=8'h47;
parameter set7=8'h48;
parameter set8=8'h49;
parameter set9=8'h4A;
parameter set10=8'h4B;
parameter set11=8'h4C;
parameter nul=8'h4D;
parameter nulr=8'hFF;
assign LCD_N=0;
assign LCD_P=1;
always @(posedge clk)
begin
counter<=counter+1;
if(counter==16'b1100001101001111)
clkr<=~clkr;
end
always @(posedge clkr)
begin
assign current=next;
case(current)
set0: begin rs<=0; dat<=8'h38; next<=set1; end
set1: begin rs<=0; dat<=8'h0C; next<=set2; end
set2: begin rs<=0; dat<=8'h06; next<=set3; end
set3: begin rs<=0; dat<=8'h01; next<=set4; end
set4: begin rs<=0; dat<=8'h80; next<=dat0; end
dat0: begin rs<=1; dat<="N"; next<=dat1; end
dat1: begin rs<=1; dat<="E"; next<=dat2; end
dat2: begin rs<=1; dat<="W"; next<=dat3; end
dat3: begin rs<=1; dat<=":"; next<=dat4; end
dat4: begin rs<=1; dat<="1"; next<=dat5; end
dat5: begin rs<=1; dat<="2"; next<=dat6; end
dat6: begin rs<=1; dat<="3"; next<=dat7; end
dat7: begin rs<=1; dat<="."; next<=dat8; end
dat8: begin rs<=1; dat<="4"; next<=dat9; end
dat9: begin rs<=1; dat<="5"; next<=dat10; end
dat10: begin rs<=1; dat<="6"; next<=dat11; end
dat11: begin rs<=1; dat<="M"; next<=dat12; end
dat12: begin rs<=1; dat<="H"; next<=dat13; end
dat13: begin rs<=1; dat<="Z"; next<=set5; end
set5: begin rs<=0;dat<=8'hC0;next<=dat14; end//设置第2行地址
dat14: begin rs<=1; dat<="O"; next<=dat15; end
dat15: begin rs<=1; dat<="L"; next<=dat16; end
dat16: begin rs<=1; dat<="D"; next<=dat17; end
dat17: begin rs<=1; dat<=":"; next<=dat18; end
dat18: begin rs<=1; dat<="7"; next<=dat19; end
dat19: begin rs<=1; dat<="8"; next<=dat20; end
dat20: begin rs<=1; dat<="9"; next<=dat21; end
dat21: begin rs<=1; dat<="."; next<=dat22; end
dat22: begin rs<=1; dat<="3"; next<=dat23; end
dat23: begin rs<=1; dat<="4"; next<=dat24; end
dat24: begin rs<=1; dat<="5"; next<=dat25; end
dat25: begin rs<=1; dat<="M"; next<=dat26; end
dat26: begin rs<=1; dat<="H"; next<=dat27; end
dat27: begin rs<=1; dat<="Z"; next<=nul; end
nul: begin rs<=0; dat<=8'h00; //控制指令与数据写入的次数
if(cnt！=2'h2)
begin
e<=0;next<=set0;cnt<=cnt+1;
end
else
begin next<=nul; e<=1;
end
end
default: next<=set0;
endcase
if(cnt_clkr！=9'b111110100) cnt_clkr <=cnt_clkr + 1'b1;
else
begin
assign current_clkr=next_clkr;
case(current_clkr)
set6: begin rs<=0; dat<=8'h38; next_clkr<=set7; end
set7: begin rs<=0; dat<=8'h0C; next_clkr<=set8; end
set8: begin rs<=0; dat<=8'h06; next_clkr<=set9; end
set9: begin rs<=0; dat<=8'h01; next_clkr<=set10; end
set10: begin rs<=0; dat<=8'h80; next_clkr<=dat28; end
dat28: begin rs<=1; dat<="O"; next_clkr<=dat29; end
dat29: begin rs<=1; dat<="L"; next_clkr<=dat30; end
dat30: begin rs<=1; dat<="D"; next_clkr<=dat31; end
dat31: begin rs<=1; dat<=":"; next_clkr<=dat32; end
dat32: begin rs<=1; dat<="7"; next_clkr<=dat33; end
dat33: begin rs<=1; dat<="8"; next_clkr<=dat34; end
dat34: begin rs<=1; dat<="9"; next_clkr<=dat35; end
dat35: begin rs<=1; dat<="."; next_clkr<=dat36; end
dat36: begin rs<=1; dat<="3"; next_clkr<=dat37; end
dat37: begin rs<=1; dat<="4"; next_clkr<=dat38; end
dat38: begin rs<=1; dat<="5"; next_clkr<=dat39; end
dat39: begin rs<=1; dat<="M"; next_clkr<=dat40; end
dat40: begin rs<=1; dat<="H"; next_clkr<=dat41; end
dat41: begin rs<=1; dat<="Z"; next_clkr<=set11; end
set11: begin rs<=0;dat<=8'hC0;next_clkr<=dat42; end//设置第2行地址
dat42: begin rs<=1; dat<="N"; next_clkr<=dat43; end
dat43: begin rs<=1; dat<="E"; next_clkr<=dat44; end
dat44: begin rs<=1; dat<="W"; next_clkr<=dat45; end
dat45: begin rs<=1; dat<=":"; next_clkr<=dat46; end
dat46: begin rs<=1; dat<="1"; next_clkr<=dat47; end
dat47: begin rs<=1; dat<="2"; next_clkr<=dat48; end
dat48: begin rs<=1; dat<="3"; next_clkr<=dat49; end
dat49: begin rs<=1; dat<="."; next_clkr<=dat50; end
dat50: begin rs<=1; dat<="4"; next_clkr<=dat51; end
dat51: begin rs<=1; dat<="5"; next_clkr<=dat52; end
dat52: begin rs<=1; dat<="6"; next_clkr<=dat53; end
dat53: begin rs<=1; dat<="M"; next_clkr<=dat54; end
dat54: begin rs<=1; dat<="H"; next_clkr<=dat55; end
dat55: begin rs<=1; dat<="Z"; next_clkr<=nulr; end
nulr: begin rs<=0; dat<=8'h47; //控制指令与数据写入的次数
if(cntr！=2'h2)
begin
e<=0;next_clkr<=set6;cntr<=cntr+1;
end
else
begin next_clkr<=nul; e<=1;
end
end
default: next_clkr<=set6;
endcase
end
end
assign en=clkr|e;
assign rw=0;
endmodule
module LCD1602(clk, rs, rw, en,dat,LCD_N,LCD_P);
input clk;
output [7:0] dat;
output rs,rw,en,LCD_N,LCD_P;
//tri en;
reg e;
reg [7:0] dat;
reg rs;
reg [15:0] counter;
reg [7:0] current,next,current_clkr,next_clkr;
reg clkr;
reg [1:0] cnt=2'b00,cntr=2'b00;
reg [8:0] cnt_clkr=9'b0;
parameter set0=8'h00;
parameter set1=8'h01;
parameter set2=8'h02;
parameter set3=8'h03;
parameter set4=8'h04;
parameter set5=8'h05;
parameter dat0=8'h06;
parameter dat1=8'h07;
parameter dat2=8'h08;
parameter dat3=8'h09;
parameter dat4=8'h0A;
parameter dat5=8'h0B;
parameter dat6=8'h0C;
parameter dat7=8'h0D;
parameter dat8=8'h0E;
parameter dat9=8'h0F;
parameter dat10=8'h10;
parameter dat11=8'h11;
parameter dat12=8'h12;
parameter dat13=8'h13;
parameter dat14=8'h14;
parameter dat15=8'h15;
parameter dat16=8'h16;
parameter dat17=8'h17;
parameter dat18=8'h18;
parameter dat19=8'h19;
parameter dat20=8'h1A;
parameter dat21=8'h1B;
parameter dat22=8'h1C;
parameter dat23=8'h1D;
parameter dat24=8'h1E;
parameter dat25=8'h1F;
parameter dat26=8'h20;
parameter dat27=8'h2A;
parameter dat28=8'h2B;
parameter dat29=8'h2C;
parameter dat30=8'h2D;
parameter dat31=8'h2E;
parameter dat32=8'h2F;
parameter dat33=8'h30;
parameter dat34=8'h31;
parameter dat35=8'h32;
parameter dat36=8'h33;
parameter dat37=8'h34;
parameter dat38=8'h35;
parameter dat39=8'h36;
parameter dat40=8'h37;
parameter dat41=8'h38;
parameter dat42=8'h39;
parameter dat43=8'h3A;
parameter dat44=8'h3B;
parameter dat45=8'h3C;
parameter dat46=8'h3D;
parameter dat47=8'h3D;
parameter dat48=8'h3F;
parameter dat49=8'h40;
parameter dat50=8'h41;
parameter dat51=8'h42;
parameter dat52=8'h43;
parameter dat53=8'h44;
parameter dat54=8'h45;
parameter dat55=8'h46;
parameter set6=8'h47;
parameter set7=8'h48;
parameter set8=8'h49;
parameter set9=8'h4A;
parameter set10=8'h4B;
parameter set11=8'h4C;
parameter nul=8'h4D;
parameter nulr=8'hFF;
assign LCD_N=0;
assign LCD_P=1;
always @(posedge clk)
begin
counter<=counter+1;
if(counter==16'b1100001101001111)
clkr<=~clkr;
end
always @(posedge clkr)
begin
assign current=next;
case(current)
set0: begin rs<=0; dat<=8'h38; next<=set1; end
set1: begin rs<=0; dat<=8'h0C; next<=set2; end
set2: begin rs<=0; dat<=8'h06; next<=set3; end
set3: begin rs<=0; dat<=8'h01; next<=set4; end
set4: begin rs<=0; dat<=8'h80; next<=dat0; end
dat0: begin rs<=1; dat<="N"; next<=dat1; end
dat1: begin rs<=1; dat<="E"; next<=dat2; end
dat2: begin rs<=1; dat<="W"; next<=dat3; end
dat3: begin rs<=1; dat<=":"; next<=dat4; end
dat4: begin rs<=1; dat<="1"; next<=dat5; end
dat5: begin rs<=1; dat<="2"; next<=dat6; end
dat6: begin rs<=1; dat<="3"; next<=dat7; end
dat7: begin rs<=1; dat<="."; next<=dat8; end
dat8: begin rs<=1; dat<="4"; next<=dat9; end
dat9: begin rs<=1; dat<="5"; next<=dat10; end
dat10: begin rs<=1; dat<="6"; next<=dat11; end
dat11: begin rs<=1; dat<="M"; next<=dat12; end
dat12: begin rs<=1; dat<="H"; next<=dat13; end
dat13: begin rs<=1; dat<="Z"; next<=set5; end
set5: begin rs<=0;dat<=8'hC0;next<=dat14; end//设置第2行地址
dat14: begin rs<=1; dat<="O"; next<=dat15; end
dat15: begin rs<=1; dat<="L"; next<=dat16; end
dat16: begin rs<=1; dat<="D"; next<=dat17; end
dat17: begin rs<=1; dat<=":"; next<=dat18; end
dat18: begin rs<=1; dat<="7"; next<=dat19; end
dat19: begin rs<=1; dat<="8"; next<=dat20; end
dat20: begin rs<=1; dat<="9"; next<=dat21; end
dat21: begin rs<=1; dat<="."; next<=dat22; end
dat22: begin rs<=1; dat<="3"; next<=dat23; end
dat23: begin rs<=1; dat<="4"; next<=dat24; end
dat24: begin rs<=1; dat<="5"; next<=dat25; end
dat25: begin rs<=1; dat<="M"; next<=dat26; end
dat26: begin rs<=1; dat<="H"; next<=dat27; end
dat27: begin rs<=1; dat<="Z"; next<=nul; end
nul: begin rs<=0; dat<=8'h00; //控制指令与数据写入的次数
if(cnt！=2'h2)
begin
e<=0;next<=set0;cnt<=cnt+1;
end
else
begin next<=nul; e<=1;
end
end
default: next<=set0;
endcase
if(cnt_clkr！=9'b111110100) cnt_clkr <=cnt_clkr + 1'b1;
else
begin
assign current_clkr=next_clkr;
case(current_clkr)
set6: begin rs<=0; dat<=8'h38; next_clkr<=set7; end
set7: begin rs<=0; dat<=8'h0C; next_clkr<=set8; end
set8: begin rs<=0; dat<=8'h06; next_clkr<=set9; end
set9: begin rs<=0; dat<=8'h01; next_clkr<=set10; end
set10: begin rs<=0; dat<=8'h80; next_clkr<=dat28; end
dat28: begin rs<=1; dat<="O"; next_clkr<=dat29; end
dat29: begin rs<=1; dat<="L"; next_clkr<=dat30; end
dat30: begin rs<=1; dat<="D"; next_clkr<=dat31; end
dat31: begin rs<=1; dat<=":"; next_clkr<=dat32; end
dat32: begin rs<=1; dat<="7"; next_clkr<=dat33; end
dat33: begin rs<=1; dat<="8"; next_clkr<=dat34; end
dat34: begin rs<=1; dat<="9"; next_clkr<=dat35; end
dat35: begin rs<=1; dat<="."; next_clkr<=dat36; end
dat36: begin rs<=1; dat<="3"; next_clkr<=dat37; end
dat37: begin rs<=1; dat<="4"; next_clkr<=dat38; end
dat38: begin rs<=1; dat<="5"; next_clkr<=dat39; end
dat39: begin rs<=1; dat<="M"; next_clkr<=dat40; end
dat40: begin rs<=1; dat<="H"; next_clkr<=dat41; end
dat41: begin rs<=1; dat<="Z"; next_clkr<=set11; end
set11: begin rs<=0;dat<=8'hC0;next_clkr<=dat42; end//设置第2行地址
dat42: begin rs<=1; dat<="N"; next_clkr<=dat43; end
dat43: begin rs<=1; dat<="E"; next_clkr<=dat44; end
dat44: begin rs<=1; dat<="W"; next_clkr<=dat45; end
dat45: begin rs<=1; dat<=":"; next_clkr<=dat46; end
dat46: begin rs<=1; dat<="1"; next_clkr<=dat47; end
dat47: begin rs<=1; dat<="2"; next_clkr<=dat48; end
dat48: begin rs<=1; dat<="3"; next_clkr<=dat49; end
dat49: begin rs<=1; dat<="."; next_clkr<=dat50; end
dat50: begin rs<=1; dat<="4"; next_clkr<=dat51; end
dat51: begin rs<=1; dat<="5"; next_clkr<=dat52; end
dat52: begin rs<=1; dat<="6"; next_clkr<=dat53; end
dat53: begin rs<=1; dat<="M"; next_clkr<=dat54; end
dat54: begin rs<=1; dat<="H"; next_clkr<=dat55; end
dat55: begin rs<=1; dat<="Z"; next_clkr<=nulr; end
nulr: begin rs<=0; dat<=8'h47; //控制指令与数据写入的次数
if(cntr！=2'h2)
begin
e<=0;next_clkr<=set6;cntr<=cntr+1;
end
else
begin next_clkr<=nul; e<=1;
end
end
default: next_clkr<=set6;
endcase
end
end
assign en=clkr|e;
assign rw=0;
endmodule
同问~~~相同的问题！求解答~求解答~谢谢大神~
时序不满足，1s时间过长
先指明一下，assign语句不能在always语句里使用
你程序重新改写吧，写成状态机，你这种程序完全是受cpu的那种运行方式写的，而fpga是并发的，不需要再在一个过程里面执行多个条件语句，采取多过程才是合适的
您好，请看我的私信，我已经将改写的程序给您发过去，但是还是有问题。
这里面的next<=nul改成next<=set4,那我后面的那一堆就可以不要了吗?一直更改地址，那为什么不弄到next<=set0呢?不需要清屏吗?
大神我的消息数量已经到达最大数量了，能不能加你QQ或者微信聊一下
我的qq号1417075248
任何一个初始化过程只需要一次，nul的当然可以不要