ISE环境下使用Verilog设计RAM写模块出现问题
时间：10-02
整理：3721RD
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把Quartus环境下调试正确的RAM读写模块在ISE14.7中重新综合后出现问题，RAM读部分正常，RAM写部分出现问题如下：Par:288 - The signal ram_addr_bus _IBUF has no load. PAR will not attempt to route this signal.
Par:288 - The signal data_in_bus _IBUF has no load. PAR will not attempt to route this signal.
Par:288 - The signal data_in_bus _IBUF has no load. PAR will not attempt to route this signal.