Quartus编译报错Gate Level Simulation Netlist not found

大四电路女一枚，做毕设时，全编译一直出现Error: Gate Level Simulation Netlist not found -- run EDA NetList Writer to generate Gate Level simulation netlist这样的错误，单独点击EDA Netlist就没有错误可以通过，只要全编译就报错。求解答?

能截个图来看一下吗