VHDL 闹钟系统设计
时间:10-02
整理:3721RD
点击:
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- PACKAGE P_ALARM IS
- SUBTYPE T_DIGITAL IS INTEGER RANGE 0 TO 9;
- SUBTYPE T_SHORT IS INTEGER RANGE 0 TO 65535;
- TYPE T_CLOCK_TIME IS ARRAY (3 DOWNTO 0) OF T_DIGITAL;
- TYPE T_DISPLAY IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
- TYPE SEG7 IS ARRAY (0 TO 9) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
- CONSTANT SEVEN_SEG: SEG7 :=("0111111",
- "0000110",
- "1011011",
- "1001111",
- "1100110",
- "1101101",
- "1111101",
- "0000111",
- "1111111",
- "1110011"
- );
黑体行的数据类型声明有问题吗,创建元件符号或者例化语句时会出错。网上几乎所有VHDL写的闹钟系统都是这样的,有人用quartus Ⅱ仿真成功的吗?
太假了吧
这要能对,母猪上树
http://pan.baidu.com/s/1eQGOiky
我自己写的多功能闹钟 你看看