verilog 语法错误： A begin/end block was found with an empty body.

就是一个很普通的4位计数器，不知道是什么错误，脑浆都要爆出来了
经常会出现这个错误提示：
A begin/end block was found with an empty body.

module counter_4(Q, clk, clr);
input clk, clr;
output Q;
reg [3:0] Q;
always @(posedge clk)
begin
  if(clr)
    Q <= 4'b0;
  else
    Q <= Q + 1;
end
endmodule

`define FALSE 1'b0;
`define TRUE 1'b1;
module counter_4_tb;
wire [3:0] count;
reg CLOCK, CLEAR;
counter_4 counter(count, CLOCK, CLEAR);
initial
  $monitor($time, "count = %b", count);
// set CLOCK
initial
begin
  CLOCK = `TRUE;
  forever #5 CLOCK = ~CLOCK;
end
// set CLEAR
initial
begin
  CLEAR = `TRUE;
  repeat (5) @(negedge CLOCK);
  CLEAR = `FALSE;
end
endmodule
** error: G:/Program Files (x86)/modeltech64_10.1c/examples/counter_4_tb.v(17): A begin/end block was found with an empty body.  This is permitted in SystemVerilog, but not permitted in Verilog.  Please look for any stray semicolons.
** error: G:/Program Files (x86)/modeltech64_10.1c/examples/counter_4_tb.v(24): A begin/end block was found with an empty body.  This is permitted in SystemVerilog, but not permitted in Verilog.  Please look for any stray semicolons.
** error: G:/Program Files (x86)/modeltech64_10.1c/examples/counter_4_tb.v(26): A begin/end block was found with an empty body.  This is permitted in SystemVerilog, but not permitted in Verilog.  Please look for any stray semicolons.

顶下，高手们帮个忙！

`define FALSE 1'b0
`define TRUE 1'b1
不要加分号！

把第一组begin end去掉试试