VHDL 错误显示error:can't determine definition of operator rol

1. library ieee;
   
2. use ieee.std_logic_1164.all;
   
3. use ieee.std_logic_unsigned.all;
   
4. use ieee.std_logic_arith.all;
   
5. entity yimaqi2 is
   
6.         port(a,b,c,e,f,g:in std_logic;
   
7.                  y:out std_logic_vector(7 downto 0));
   
8. end entity yimaqi2;
   
9. architecture LSyimaqi of yimaqi2 is
   
10. signal sem:std_logic_vector(2 downto 0);
    
11. begin
    
12. sem<=c&b&a;
    
13. process(sem,e,f,g)
    
14. variable h:std_logic_vector(7 downto 0);
    
15. begin
    
16. h:="11111110";
    
17. if(e='1'and f='0'and g='0')then
    
18. y<=h rol conv_integer(sem);
    
19. else
    
20.         y<="11111111";
    
21. end if;
    
22. end process;
    
23. end architecture LSyimaqi;
    

好像是没定义rol,