pwm,大神帮忙解释一下这段程序
时间:10-02
整理:3721RD
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程序中英文缩写都代表什么意思呢?这段程序实现什么功能呢?
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fcounter is
generic
(
f_len:natural:=9;
f_delta:natural:=10
);
port(
rst,clk,di:in std_logic;
f,fi:out std_logic_vector(f_len-1 downto 0);
tm:out std_logic
);
end entity fcounter ;
architecture bhv of fcounter is
type f_reg_type is array (natural range ) of std_logic_vector(f_len-1 downto 0);
signal f_reg:f_reg_type(2+2 downto 0);
signal fsum:std_logic_vector(f_len-1+2 downto 0);
signal di_reg:std_logic_vector(3 downto 0);
signal di_rise,di_fall:std_logic;
signal cnt:std_logic_vector(f_len-1 downto 0);
begin
fsum '0');
f_reg (others=>'0'));
cnt '0');
tm '0');
tm '0');
tm f_reg(4) and f_reg(3)-f_delta f_reg(4)) then
f_reg(2 downto 0)<=f_reg(1 downto 0)&(f_reg(3)+f_reg(4));
end if;
end if;
end process;
di_rise<= '1' when (di_reg(2)='0' and di_reg(1)='0'and di_reg(0)='1' and di='1') else '0';
di_fall<= '1' when (di_reg(2)='1' and di_reg(1)='1'and di_reg(0)='0' and di='0') else '0';
end bhv;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fcounter is
generic
(
f_len:natural:=9;
f_delta:natural:=10
);
port(
rst,clk,di:in std_logic;
f,fi:out std_logic_vector(f_len-1 downto 0);
tm:out std_logic
);
end entity fcounter ;
architecture bhv of fcounter is
type f_reg_type is array (natural range ) of std_logic_vector(f_len-1 downto 0);
signal f_reg:f_reg_type(2+2 downto 0);
signal fsum:std_logic_vector(f_len-1+2 downto 0);
signal di_reg:std_logic_vector(3 downto 0);
signal di_rise,di_fall:std_logic;
signal cnt:std_logic_vector(f_len-1 downto 0);
begin
fsum '0');
f_reg (others=>'0'));
cnt '0');
tm '0');
tm '0');
tm f_reg(4) and f_reg(3)-f_delta f_reg(4)) then
f_reg(2 downto 0)<=f_reg(1 downto 0)&(f_reg(3)+f_reg(4));
end if;
end if;
end process;
di_rise<= '1' when (di_reg(2)='0' and di_reg(1)='0'and di_reg(0)='1' and di='1') else '0';
di_fall<= '1' when (di_reg(2)='1' and di_reg(1)='1'and di_reg(0)='0' and di='0') else '0';
end bhv;