哪位大神帮忙看看程序为什么出错？VHDL写的状态机

本人新手，这是书上的例子，怎么会编译不成功?
library ieee;
use std_logic_1164.all;
entity chop8_1 is
port(d,rst,clk: in bit;
q: out bit);
end chop8_1;
architecture chop of chop8_1 is
type state is (zero,one,two,three);
signal pr_state, nx_state: state;
begin
--lower section--
process(clk,rst)
begin
if (rst='1') then
pr_state
q
q
q
q<='1';
if (d='0') then nx_state<=zero;
else nx_state<=three;
end if;
end case;
end process;
end chop;
Error (10482): VHDL error at chop8_1.vhd(2): object "std_logic_1164" is used but not declared
Error (10800): VHDL error at chop8_1.vhd(2): selected name in use clause is not an expanded name

在网上搜的，改成这样试一试！
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

额，我怎么这么粗心十分感谢！