quartus编译出错，求哪位大神帮忙看看

quartus9.0为什么有Error (10822): HDL error at kk.vhd(14): couldn't implement registers for assignments on this clock edge程序为
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tongji is
port(clk:in std_logic;
y:out std_logic_vector(3 downto 0));
end tongji;
architecture bhv  of tongji is
begin
process(clk)
variable count:std_logic_vector(3 downto 0);
begin
count:="0011";
if (clk'event and clk='0') then
        if(count<=9) then count:=count+1;
        else count:="0000";
        end if;
end if;
y<=count;
end process;
end bhv;

错误时：无法实现寄存器分配在这个时钟的边缘   if (clk'event and clk='0') then