使用modelsim10.1编译xilinx ddr3_model_parameters_c3.vh出问题
时间：10-02
整理：3721RD
点击：
** Error: E:\ddr3_sim\src\coregen\ddr3_model_parameters_c3.vh(1509): (vlog-2155) Global declarations are illegal in Verilog 2001 syntax.
** Error: E:\ddr3_sim\src\coregen\ddr3_model_parameters_c3.vh(1713): (vlog-2730) Undefined variable: 'TIS'.
** Error: E:\ddr3_sim\src\coregen\ddr3_model_parameters_c3.vh(1713): 'TIS' already declared in this scope (work).
** Error: E:\ddr3_sim\src\coregen\ddr3_model_parameters_c3.vh(1713): Verilog Compiler exiting
求大神指教怎么改
** Error: E:\ddr3_sim\src\coregen\ddr3_model_parameters_c3.vh(1713): (vlog-2730) Undefined variable: 'TIS'.
** Error: E:\ddr3_sim\src\coregen\ddr3_model_parameters_c3.vh(1713): 'TIS' already declared in this scope (work).
** Error: E:\ddr3_sim\src\coregen\ddr3_model_parameters_c3.vh(1713): Verilog Compiler exiting
求大神指教怎么改