小白求助avalon总线和CY7C68013A接口代码问题

时间：10-02 整理：3721RD 点击：

module USB(clk,
                  reset_n,
                  chipselect_n,
                  address,
                  read_n,
                  read_data,
                  write_n,
                  write_data,
                  redyfordata,
                  dataavailable,
                  endofpacket,

                  usb_ifclk,
                  usb_slrd_n,
                  usb_slwr_n,
                  usb_sloe_n,
                  usb_flagb,
                  usb_flagc,
                  usb_pkend,
                  usb_data,
                  usb_address,
                  usb_clk);
//----------------------------------------------------------------
input clk,usb_clk;
input reset_n;
input chipselect_n;
input [1:0]address;

input read_n;
output [31:0]read_data;
input write_n;
input [31:0]write_data;
//---------------------------------
output redyfordata;
output dataavailable;
output endofpacket;
//---------------------------------
output usb_ifclk;
output usb_slrd_n;
output usb_slwr_n;
output usb_sloe_n;
input usb_flagb;
input usb_flagc;
output usb_pkend;
inout  [15:0]usb_data;
output [1:0]usb_address;
reg usb_sloe_n;
reg [1:0]usb_address;
//----------------------------------------------------------------
//reg [15:0]pkendcount;
//----------------------------------------------------------------
parameter USB_IDLE = 4'd0;
parameter USB_RIREADY = 4'd1;
parameter USB_WIREADY = 4'd2;
parameter USB_RDATA = 4'd3;
parameter USB_WDATA = 4'd4;
//parameter USB_PKEND = 3'd5;
//----------------------------------------------------------------
reg [3:0] STATE_NUM;
//parameter ENDPOINT2  = 2'b00;
//parameter ENDPOINT4  = 2'b01;
//parameter ENDPOINT6  = 2'b10;
//parameter ENDPOINT8  = 2'b11;
//----------------------------------------------------------------
//wire [9:0] w_wrusedw;
//----------------------------------------------------------------
//wire [31:0] r_q;
//wire [9:0] r_rdusedw;
//wire r_rdreq;
//wire ru_wrreq;
//wire ru_wrfull;
//wire wu_rdempty;
//wire w_wrreq;
//wire [15:0] wu_q;
//wire wu_rdreq;
reg rul;
reg [7:0]num;
always@(posedge usb_ifclk or negedge reset_n)
begin
if (reset_n ！= 1'b1) begin
                        STATE_NUM <= USB_IDLE;
                        rul<= 1'd1;
                        usb_sloe_n<=1'd1;
                        num<=8'h0;
                        end
else begin
         case(STATE_NUM)
         USB_IDLE: begin
                              rul<=~rul;
                              num<=8'hff;
                              if(rul)
                                 begin
                                 if(usb_flagb)
                                    begin
                                    STATE_NUM<=USB_RDATA;
                                    usb_address<=2'b00;
                                    usb_sloe_n<=1'd0;
                                    end
                                 end
                              else
                                 begin
                                 if(usb_flagc)
                                    begin
                                    STATE_NUM<=USB_WDATA;
                                    usb_address<=2'b10;
                                    end
                                 end
                        end
         USB_RDATA: begin
                        if(num==8'h0)
                              begin
                              STATE_NUM<=USB_IDLE;
                              usb_sloe_n<=1'd1;
                              end
                        else num<=num-8'h1;
                        end
         USB_WDATA: begin
                        if(num==8'h0)
                              begin
                              STATE_NUM<=USB_IDLE;
                              end
                        else num<=num-8'h1;
                        end
         default:;
         endcase
         end
end
//assign wu_rdreq = (reset_n && wu_rdempty == 1'b0 && usb_flagc == 1'b1 && usb_address==2'b10 && STATE_NUM == USB_WDATA)?1'b1:1'b0;
//assign w_wrreq = (chipselect_n == 1'b0 && write_n == 1'b0 && address==2'b00)?1'b1:1'b0;
//assign ru_wrreq = (reset_n && ru_wrfull == 1'b0 && usb_flagb == 1'b1 && usb_address==2'b00 && STATE_NUM == USB_RDATA)?1'b1:1'b0;
//assign r_rdreq = (chipselect_n == 1'b0 && read_n == 1'b0 && address==2'b00)?1'b1:1'b0;
assign read_data=(chipselect_n==1'b0 && read_n==1'b0 && address==usb_address)?usb_data:32'h0;
assign usb_slrd_n=~(reset_n && usb_flagb == 1'b1 && usb_address==2'b00 && STATE_NUM == USB_RDATA)?1'b1:1'b0;
assign usb_slwr_n=~(reset_n && usb_flagc == 1'b1 && usb_address==2'b10 && STATE_NUM == USB_WDATA)?1'b1:1'b0;
//----------------------------------------------------------------
assign endofpacket=1'b0;
assign redyfordata=  1'b1;
assign dataavailable=  1'b1;
//----------------------------------------------------------------
assign usb_pkend=1'b1;
//----------------------------------------------------------------
assign usb_ifclk=usb_clk;
//----------------------------------------------------------------
assign usb_data= (STATE_NUM == USB_WDATA)?write_data:16'hzzzz;
endmodule
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