testbench时钟信号

testbench时钟信号的编写  

2011-01-13 11:07:38|  分类： FPGA的分享 |  标签：clock  parameter  reg  占空比 time_period  |举报|字号订阅

/*******************************************************

     时钟信号的编写

*******************************************************/

'timescale 1ns/1ps //定义 时间单位/时间精度

/******************占空比50%(采用initial)**************/

parameter TIME_PERIOD = 10;

reg clock;

initial

begin

clock = 0;//初始化clock为0

forever

   #(TIME_PERIOD/2) clock = ~clock;

end

/******************占空比50%(采用always)***************/

parameter TIME_PERIOD = 10;

reg clock;

initial

clock = 0;//初始化clock为0

always

# (TIME_PERIOD/2) clock = ~clock;

/******************非50%占空比(采用always)*************/

parameter HI_TIME = 5,

   LO_TIME = 10;

reg clock;

always

begin

# HI_TIME clock = 0;

# LO_TIME clock = 1;

end

/***********固定数目时钟占空比50%(采用initial)*********/

parameter PULSE_COUNT = 4,

   TIME_PERIOD = 10;

reg clock;

initial

begin

clock = 0;//初始化clock为0

repeat (2*PULSE_COUNT)

   #(TIME_PERIOD/2) clock = ~clock;

end

/****************相移时钟信号(采用always)**************/

parameter HI_TIME = 5,

   LO_TIME = 10,

   PHASE_SHIFT = 2;

reg  absolute_clock;

wire derived_clock;

always

begin

# HI_TIME absolute_clock = 0;

# LO_TIME absolute_clock = 1;

end

assign # PHASE_SHIFT derived_clock =absolute_clock;