DECODER5-32有错,新手,希望得到帮助
时间:10-02
整理:3721RD
点击:
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- use ieee.std_logic_arith.all;
- entity decoder5_32 is
- port(e,f,g,h:in std_logic;
- enable:in std_logic;
- yy:out std_logic_vector(31 downto 0);
- );
- end entity decoder5_32;
- architecture art5_32 of decoder5_32 is
- component decoder4_16 is
-
- PORT (a:IN STD_LOGIC;
- b:IN STD_LOGIC;
- c:IN STD_LOGIC;
- d:IN STD_LOGIC;
- en:IN STD_LOGIC;
- y:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
- );
- end component deccoder4_16;
-
- begin
- U1:decoder4_16 port map(a=>e,b=>f,c=>g,d=>h,en=>enable,y=>yy(31 downto 16));
- U2:decoder4_16 port map(a=>e,b=>f,c=>g,d=>h,not en=>enable,y=>yy(15 downto 0));
- end architecture art5_32;
Error (10500): VHDL syntax error at decoder5_32.vhd(21) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"
-----------------------------------
下面是decoder4-16
- LIBRARY IEEE;
- USE IEEE.STD_LOGIC_1164.ALL;
- USE IEEE.STD_LOGIC_ARITH.ALL;
- USE IEEE.STD_LOGIC_UNSIGNED.ALL;
- ENTITY decoder4_16 IS
- PORT (a:IN STD_LOGIC;
- b:IN STD_LOGIC;
- c:IN STD_LOGIC;
- d:IN STD_LOGIC;
- en:IN STD_LOGIC;
- y:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
- END ENTITY decoder4_16;
- ARCHITECTURE ar1 OF decoder4_16 IS
- SIGNAL si1:STD_LOGIC_VECTOR(4 DOWNTO 0);
- BEGIN
- si1<=en & d & c & b & a;
- WITH si1 SELECT
- y<="1111111111111110"WHEN"10000",
- "1111111111111101"WHEN"10001",
- "1111111111111011"WHEN"10010",
- "1111111111110111"WHEN"10011",
- "1111111111101111"WHEN"10100",
- "1111111111011111"WHEN"10101",
- "1111111110111111"WHEN"10110",
- "1111111101111111"WHEN"10111",
- "1111111011111111"WHEN"11000",
- "1111110111111111"WHEN"11001",
- "1111101111111111"WHEN"11010",
- "1111011111111111"WHEN"11011",
- "1110111111111111"WHEN"11100",
- "1101111111111111"WHEN"11101",
- "1011111111111111"WHEN"11110",
- "0111111111111111"WHEN"11111",
- "1111111111111111"WHEN OTHERS;
- END ARCHITECTURE ar1;
(标注红丝部分)定义最后的这个分号是不需要的
这个not不能这样直接使用。需要现在别处处理或者在子程序中处理。