vhdl 程序为什么得不到将位数分离的结果

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity xuanze is
port( s,c:in integer range 0000 to 9999;
      s1,s2,s3,s4,c1,c2,c3,c4:buffer integer range 0 to 9);
end;      
architecture one of xuanze is
   signal a1,a2,a3,a4,b1,b2,b3,b4:integer:=0;
   
    signal a:integer:=s;
    signal b:integer:=c;
begin
    process(a,b)
    begin   
    if(a>999 and a 99 and a 9 and a 999 and b 99 and b 9and b 999 and a 99 and a 9 and a 999 and b 99 and b 9 and b<=99) then
          c1<=0;
          c2<=0;
          c3<=b / 10;
          c4<=(b rem 10);
      else
          c1<=0;
          c2<=0;
          c3<=0;
         c4<=b;
end if;
    end process;
    end one;
你可以再试试

小编的程序只能分离出最高位 建议使用多个变量进行结果保存