流水灯程序
时间：10-02
整理：3721RD
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module liushuideng( sys_clk,LED);
input sys_clk;
output [7:0] LED;
reg[8:0] LED_out;
reg[8:0] LED_out1;
reg[25:0] count;
always @(posedge sys_clk )
begin
count=count+1;
if(count==26'd25000000)begin
LED_out=LED_out>>1;
if(LED_out==9'b000000000)
LED_out=9'b111111111;
LED_out1=~LED_out;
end
end
assign LED=LED_out1[7:0];
endmodule
求解，为什么寄存器reg LED_out，LED_out1要是九位的，换成八位后流水灯只循环量七个灯?
input sys_clk;
output [7:0] LED;
reg[8:0] LED_out;
reg[8:0] LED_out1;
reg[25:0] count;
always @(posedge sys_clk )
begin
count=count+1;
if(count==26'd25000000)begin
LED_out=LED_out>>1;
if(LED_out==9'b000000000)
LED_out=9'b111111111;
LED_out1=~LED_out;
end
end
assign LED=LED_out1[7:0];
endmodule
求解，为什么寄存器reg LED_out，LED_out1要是九位的，换成八位后流水灯只循环量七个灯?
非常好的资源，小弟学习了
Verilog还不会呢我
看懂了些，，嘻嘻嘻
你确定流水了，我的是全亮