verilog 一个简单程序 报错，求解

按照时钟 控制abcd四个量的输出，但是map 时出错：
Pack:198 - NCD was not produced.  All logic was removed from the design.
   This is usually due to having no input or output PAD connections in the
   design and no nets or symbols marked as 'SAVE'.  You can either add PADs or
   'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
   the mapper.  For more information on trimming issues search the Xilinx
   Answers database for "ERROR:Pack:198" and read the Master Answer Record for
   MAP Trimming Issues.
请教
module LCD(a,b,c,d,clk
    );
output a,b,c,d;
input clk;
reg [25:0] count;
reg a,b,c,d;
// 初始化
initial
begin
        a=1;b=1;c=1;d=1;
        count=0;
        end
// 通过系统时钟控制变量count
       
always @(posedge clk)
begin
        count<=count+1;
   end
//通过count 计数，实现abcd四个变量的取反
       
always @(count [25:21])
begin
        a<=~a;b<=~b;c<=~c;d<=~d;
        end
endmodule

你这个程序貌似不能综合吧，怎么map啊！