ADS仿真VCO时遇到不收敛（convergence）

我现在在做一个锁相环，用ADS仿真vco（用变容二极管和电感，再加上后级隔离）。
在transient仿真时，经常会遇到报错，“Convergence failure during transient analysis at time = XXX”
ADS我用的不熟，感觉是不收敛造成的。并且有时把仿真的间隔时间（steptime）变大，就不报错了。
请大侠指教！我的电路是不是有问题?该如何改?多谢！

自己再顶一下啊！
请高手赐教！

这个仿真器的问题。
在Cadence中也经常会有不收敛的问题，但是如果修改step time
，就会好一些

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谢谢！
我发现修改step time会影响仿真结果，尤其在step time和VCO输出信号的周期可比拟的时候。
比如vco输出频率为500M（周期2ns），我将ADS仿真的时间设为2ns和1ns所出的结果完全不一样。如果设为0.5ns，结果又有变化，且在100多ns的地方不收敛，设为0.25ns，在30ns的地方不收敛。
还请高手指点，step time该如何设置?
多谢！

step time设置小点试试（远小于周期），这样仿出来的会准点，但仿真时间会长点。
stop time 是信号周期的几倍就好了。

再看看电路原理上还有什么问题

the step settings should be smaller than 1/2*f for transient simulator, where f is the frequency you are interested; so you settings of tstep = 2ns is definitely wrong, tstep = 0.25ns is a good choice.
usually convergence problem is caused by circuit design problems, very much likely strong harmonic components are induced, or vco is unstable and can not converge;
unless you want to identify if vco can be stimulate into stable status or nor, it is suggested to use envelope simulator for instead, which is much faster and easy to harmonic components identification; the simulation accuracy can be comparable with transient simulator

好像step设置不同会产生不同的结果