没有错误，为什么还是不能生成网表？
时间：10-02
整理：3721RD
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我的设计已经没有错误，session log也没有报错，但是就是把生成网表的过程给终止掉了，太诡异了
********************************************************************************
** Netlisting the design
********************************************************************************
Design Name:
E:\cadence\RF7021\rf7021.dsn
Netlist Directory:
E:\CADENCE\RF7021
Configuration File:
C:\Cadence\PSD_15.1\tools\capture\allegro.cfg
Spawning... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "E:\cadence\RF7021\rf7021.dsn" -n "E:\CADENCE\RF7021" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Aborting Netlisting... Please correct the above errors and retry.
Exiting... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "E:\cadence\RF7021\rf7021.dsn" -n "E:\CADENCE\RF7021" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
*** Done ***
没有错误为什么还要终止啊，哪位牛人指点一下，help
********************************************************************************
** Netlisting the design
********************************************************************************
Design Name:
E:\cadence\RF7021\rf7021.dsn
Netlist Directory:
E:\CADENCE\RF7021
Configuration File:
C:\Cadence\PSD_15.1\tools\capture\allegro.cfg
Spawning... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "E:\cadence\RF7021\rf7021.dsn" -n "E:\CADENCE\RF7021" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Aborting Netlisting... Please correct the above errors and retry.
Exiting... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "E:\cadence\RF7021\rf7021.dsn" -n "E:\CADENCE\RF7021" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
*** Done ***
没有错误为什么还要终止啊，哪位牛人指点一下，help
最好提供原理图，不然分析比较困难
元件没加封装，加上封装还不行的话，新建一个DESIGN，将所有图拷贝到新建DESIGN下生成NETLIST